Epson Research and Development
Page 81
Vancouver Design Center
7.5 Display Interface
7.5.1 Single Monochrome 4-Bit Panel Timing
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
LINE1
LINE2
LINE3
LINE4
LINE239 LINE240
LINE1
LINE2
FPDAT[7:4]
FPLINE
DRDY (MOD)
HDP
HNDP
FPSHIFT
FPDAT7
1-317
1-318
1-319
1-320
1-1
1-2
1-3
1-4
1-5
1-6
FPDAT6
FPDAT5
1-7
1-8
FPDAT4
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 320x240 panel
Figure 7-22: Single Monochrome 4-Bit Panel Timing
VDP
VNDP
HDP
= Vertical Display Period
= (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
HNDP
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
