Epson Research and Development
Page 91
Vancouver Design Center
For 8 bpp color depths, the formula must take into consideration that the blit engine accepts
only WORD accesses and each pixel is one BYTE. The blit engine needs to know whether
the first pixel of each line is stored in the low byte or high byte. This is determined by bit 0
of the Destination Start Address Register 0 (REG[108h]). If the Destination Phase is 1 (bit
0 of the Destination Start Address Register 0 is set), the first pixel of each line is placed in
the high byte of the WORD and the contents of the low byte is undefined. If the Destination
Phase is 0, the first pixel is placed in the low byte and the second pixel is placed in the high
byte. Depending on the Destination Phase and the Blit Width, the last WORD in each line
may contain only one pixel. It is always in the low byte if more than one WORD per line is
required. The number of WORD reads the blit engine expects for 8 bpp color depths is
shown in the following formula.
nWORDS
= ((BlitWidth + 1 + DestinationPhase) ÷ 2) × BlitHeight
Example 19: Read 100 x 20 pixels at the screen coordinates x = 25, y = 38 and save
to system memory. Assume a display of 640x480 at a color depth of 8
bpp.
1. Calculate the source address (upper left corner of the screen blit rectangle), using the
formula.
SourceAddress
= (y × ScreenStride) + (x × BytesPerPixel)
= (38 × 640) + (25 × 1)
= 24345
= 5F19h
where:
BytesPerPixel = 1 for 8 bpp
BytesPerPixel = 2 for 15/16 bpp
ScreenStride = DisplayWidthInPixels × BytesPerPixels = 640 for 8 bpp
Program the BitBLT Source Start Address Registers. REG[106h] is set to 00h,
REG[105h] is set to 5Fh, and REG[104h] is set to 19h.
2. Program the BitBLT Width Registers to 100 - 1. REG[111h] is set to 00h and
REG[110h] is set to 63h (99 decimal).
3. Program the BitBLT Height Registers to 20 - 1. REG[113h] is set to 00h and
REG[112h] is set to 13h (19 decimal).
4. Program the Destination Phase in the BitBLT Destination Start Address Register. In
this example, the data is WORD aligned, so the destination phase is 0. REG[108h] is
set to 0.
5. Program the BitBLT Operation to select the Read Blit. REG[103h] is set to 01h.
6. Program the BitBLT Color Format Select bit for 8 bpp operations. REG[101h] is set
to 00h.
7. Program the BitBLT Memory Offset Registers to the ScreenStride in WORDS.
Programming Notes and Examples
Issue Date: 01/02/06
S1D13506
X25B-G-003-03
EPSON [ EPSON COMPANY ]
