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S1D13506 参数 Datasheet PDF下载

S1D13506图片预览
型号: S1D13506
PDF下载: 下载PDF文件 查看货源
内容描述: S1D13506彩色LCD / CRT / TV控制器 [S1D13506 Color LCD/CRT/TV Controller]
分类和应用: 电视控制器
文件页数/大小: 696 页 / 5934 K
品牌: EPSON [ EPSON COMPANY ]
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Epson Research and Development  
Page 121  
Vancouver Design Center  
IRE  
100  
20  
Active  
Line  
Blanking  
Level  
0
40 IRE  
-20  
-40  
t1  
t2  
t3  
t4  
t5  
t6  
t7  
t8  
t9  
Blanking  
Level  
0
t10  
t11  
Equalizing Pulse  
Vertical Sync Pulse  
-40  
Start of  
Horizontal Sync  
Figure 7-52: Horizontal Timing for NTSC/PAL  
Table 7-35: Horizontal Timing for NTSC/PAL  
Symbol  
Parameter  
NTSC  
PAL  
Units  
T4SC  
t1  
t2  
t3  
t4  
t5  
t6  
t7  
t8  
(4x Subcarrier clock) period  
Front Porch  
Horizontal Sync  
Breezeway  
69.841  
note 1  
67  
9
39  
note 2  
note 4  
note 6  
910  
455  
33  
56.387  
note 1  
83  
16  
44  
note 3  
note 5  
note 6  
1135  
568 / 567  
41  
ns  
T4SC  
T4SC  
T4SC  
T4SC  
T4SC  
T4SC  
T4SC  
T4SC  
T4SC  
T4SC  
T4SC  
Color Burst  
Color Back Porch  
Horizontal Blanking  
Active Video  
Line Period  
t9  
t10  
t11  
Half Line Period  
Equalizing Pulse  
Vertical Serration  
67  
83  
1. t1  
= ((REG[053] bits[5:0]) + 1) x 8 - 7 (4 bpp, 8 bpp modes)  
= ((REG[053] bits[5:0]) + 1) x 8 - 5 (15/16 bpp modes)  
2. t5NTSC = (((REG[052] bits[5:0]) x 8) + 6) - (((REG[053] bits[5:0]) + 1) x 8) - 108 (4 bpp, 8 bpp modes)  
= (((REG[052] bits[5:0]) x 8) + 6) - (((REG[053] bits[5:0]) + 1) x 8) - 110 (15/16 bpp modes)  
3. t5PAL = (((REG[052] bits[5:0]) x 8) + 7) - (((REG[053] bits[5:0]) + 1) x 8) - 136 (4 bpp, 8 bpp modes)  
= (((REG[052] bits[5:0]) x 8) + 7) - (((REG[053] bits[5:0]) + 1) x 8) - 138 (15/16 bpp modes)  
4. t6NTSC = ((REG[052] bits[5:0]) x 8) + 6  
6. t6PAL = ((REG[052] bits[5:0]) x 8) + 7  
7. t7  
= ((REG[050] bits[6:0]) + 1) x 8  
Important:  
REG[050] and REG[052] must be programmed to satisfy the Line Period (t8).  
For NTSC, (((REG[050] bits[6:0]) + 1) x 8) + (((REG[052] bits[5:0]) x 8) + 6) = 910.  
For PAL, (((REG[050] bits[6:0]) + 1) x 8) + (((REG[052] bits[5:0]) x 8) + 7) = 1135.  
Hardware Functional Specification  
Issue Date: 01/02/06  
S1D13506  
X25B-A-001-10  
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