Epson Research and Development
Page 117
Vancouver Design Center
7.5.13 CRT Timing
VNDP
VDP
VRTC
HRTC
LINE480
LINE480
LINE1
RED,GREEN,BLUE
HRTC
HDP
HNDP1
HNDP2
1-1
1-2
1-640
RED,GREEN,BLUE
Example Timing for 640x480 CRT
Figure 7-48: CRT Timing
VDP
VNDP
HDP
= Vertical Display Period
= (REG[057h] bits [1:0], REG[056h] bits [7:0]) + 1
= (REG[058h] bits [5:0]) + 1
= ((REG[050h] bits [6:0]) + 1) × 8 Ts
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
HNDP
= HNDP1 + HNDP2= ((REG[052h] bits [5:0]) + 1) × 8 Ts
Note
The signals RED, GREEN and BLUE are analog signals from the embedded DAC and represent
the color components which make up each pixel.
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
