Page 114
Epson Research and Development
Vancouver Design Center
7.5.12 TFT/D-TFD Panel Timing
VNDP
VDP
FPFRAME
FPLINE
LINE480
LINE1
LINE480
R[5:1], G[5:0], B[5:1]
DRDY
FPLINE
HDP
HNDP1
HNDP2
FPSHIFT
DRDY
R[5:1]
G[5:0]
1-1
1-2
1-640
1-1
1-1
1-2
1-2
1-640
1-640
B[5:1]
Note: DRDY is used to indicate the first pixel
Example Timing for 640x480 panel
Figure 7-46: TFT/D-TFD Panel Timing
VDP
VNDP
HDP
= Vertical Display Period
= (REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
HNDP
= HNDP1 + HNDP2 = ((REG[034h] bits [4:0]) + 1) × 8 Ts
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06
EPSON [ EPSON COMPANY ]
