Epson Research and Development
Page 111
Vancouver Design Center
7.5.11 Dual Color 16-Bit Panel Timing with External Circuit
VDP
VNDP
FPFRAME
FPLINE
DRDY (MOD)
LINE 1/241
LINE 2/242
LINE 3/243
LINE 4/244
LINE 239/479 LINE 240/480
LINE 1/241
LINE 2/242
FPDAT[15:0]
FPLINE
DRDY (MOD)
HNDP
HDP
FPSHIFT
1-R1
1-G1
1-B1
1-R2
1-G2
1-B3
1-G 638 1-B 639
FPDAT7
FPDAT6
1-B638 1-R640
1-R639 1-G640
1-G639 1-B 640
1-B2
1-R3
1-G3
1-R4
1-G4
1-B4
FPDAT5
FPDAT4
241-
241-
241-R1 241-G2 241-B3
241-G1 241-B2 241-R4
241-B1 241-R3 241-B4
241-R 2 241-G3 241-B4
G638
B639
FPDAT3
FPDAT2
241-
241-
B638
R640
241-
241-
R639
G640
FPDAT1
FPDAT0
241-
241-
G639
B640
1-R1
1-G1
1-B1
1-R2
1-G638
1-B638
1-R639
1-G639
UD7
UD6
UD5
UD4
1-B639
1-R640
1-G640
1-B 640
1-G2
1-B2
1-R3
1-G3
UD3
UD2
UD1
UD0
241-R1
241-G1
241-B1
241-R2
241-G638
241-B638
241-R639
241-G639
LD7
LD6
LD5
LD4
241-
241-G2
241-B2
241-R3
241-G3
B639
LD3
LD2
LD1
LD0
241-
R640
241-
G640
241-
B640
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
Figure 7-43: 16-Bit Dual Color Panel Timing with External Circuit
VDP
VNDP
HDP
= Vertical Display Period
= ((REG[039h] bits [1:0], REG[038h] bits [7:0]) + 1) /2
= (REG[03Ah] bits [5:0]) + 1
= ((REG[032h] bits [6:0]) + 1) × 8 Ts
= ((REG[034h] bits [4:0]) + 1) × 8 Ts
= Vertical Non-Display Period
= Horizontal Display Period
= Horizontal Non-Display Period
HNDP
Hardware Functional Specification
Issue Date: 01/02/06
S1D13506
X25B-A-001-10
EPSON [ EPSON COMPANY ]
