Page 112
Epson Research and Development
Vancouver Design Center
UD[3:0]
LD[3:0]
TO 16-BIT
PANEL
FPDAT[7:4]
FPDAT[3:0]
UD[7:4]
LD[7:4]
Q
D
FROM
S1D13506
FPSHIFT
CK
Figure 7-44: External Circuit for Color Dual 16-Bit Panel When the Media Plug is Enabled
t1
t2
Sync Timing
FPFRAME
FPLINE
t4
t3
t5
DRDY (MOD)
Data Timing
FPLINE
t6
t7
t8
t10
t9
t12
t11
FPSHIFT
t13 t14 t15 t16
1
2
3
4
FPDAT[7:0]
Figure 7-45: Dual Color 16-Bit Panel (with External Circuit) A.C. Timing
S1D13506
X25B-A-001-10
Hardware Functional Specification
Issue Date: 01/02/06