EN29LV641H/L EN29LV640U
COMMON FLASH INTERFACE (CFI)
The common flash interface (CFI) specification outlines device and host systems software
interrogation handshake, which allows specific vendor-specified software algorithms to be used for
entire families of devices. Software support can then be device-independent, JEDEC ID-
independent, and forward- and backward-compatible for the specified flash device families. Flash
vendors can standardize their existing interfaces for long-term compatibility.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to
address 55h, any time the device is ready to read array data.
The system can read CFI information at the addresses given in Tables 5-8.The upper address bits
(A7–MSB) must be all zeros. To terminate reading CFI data, the system must write the reset
command.
The system can also write the CFI query command when the device is in the autoselect mode. The
device enters the CFI query mode and the system can read CFI data at the addresses given in
Tables 5–8. The system must write the reset command to return the device to the autoselect mode.
Table 5. CFI Query Identification String
Addresses
10h
Data
0051h
Description
11h
12h
0052h Query Unique ASCII string “QRY”
0059h
13h
14h
0002h
Primary OEM Command Set
0000h
15h
16h
0040h
Address for Primary Extended Table
0000h
17h
18h
0000h
Alternate OEM Command set (00h = none exists)
0000h
19h
1Ah
0000h
Address for Alternate OEM Extended Table (00h = none exists)
0000h
Table 6. System Interface String
Addresses
Data
Description
0027h Vcc Min (write/erase)
1Bh
DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt
0036h Vcc Max (write/erase)
1Ch
DQ7-DQ4: volt, DQ3 –DQ0: 100 millivolt
0000h Vpp Min. voltage (00h = no Vpp pin present)
0000h Vpp Max. voltage (00h = no Vpp pin present)
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
Typical timeout per single byte/word write 2N µS
0003h
0000h
Typical timeout for Min, size buffer write 2N µS (00h = not supported)
000Ah Typical timeout per individual block erase 2N ms
0000h Typical timeout for full chip erase 2N ms (00h = not supported)
0005h Max. timeout for byte/word write 2N times typical
0000h Max. timeout for buffer write 2N times typical
0002h Max. timeout per individual block erase 2N times typical
0000h Max timeout for full chip erase 2N times typical (00h = not supported)
Table 7. Device Geometry Definition
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
©2005 Eon Silicon Solution, Inc., www.essi.com.tw
14
Rev. B, Issue Date: 2005/06/27
EON [ EON SILICON SOLUTION INC. ]
