ePVP6800
VFD Controller
0 0111 11rr rrrr
07rr
JZ R
R+1 → R, skip if zero
0 → R(b)
None
None
None
None
None
2 if skip
1
0 100b bbrr rrrr
0 101b bbrr rrrr
0 110b bbrr rrrr
0 111b bbrr rrrr
0xxx
0xxx
0xxx
0xxx
BC R,b
BS R,b
JBC R,b
JBS R,b
1 → R(b)
1
if R(b)=0, skip
if R(b)=1, skip
2 if skip
2 if skip
PC+1 → [SP]
(Page, k) → PC
1 00kk kkkk kkkk
1kkk
CALL k
None
2
1 01kk kkkk kkkk
1 1000 kkkk kkkk
1 1001 kkkk kkkk
1 1010 kkkk kkkk
1 1011 kkkk kkkk
1 1100 kkkk kkkk
1 1101 kkkk kkkk
1kkk
18kk
19kk
1Akk
1Bkk
1Ckk
1Dkk
JMP k
(Page, k) → PC
k → A
None
None
Z
2
1
1
1
1
2
1
MOV A,k
OR A,k
A ∨ k → A
AND A,k
XOR A,k
RETL k
SUB A,k
A & k → A
Z
A ⊕ k → A
Z
k → A, [Top of Stack] → PC
k-A → A
None
Z,C,DC
PC+1 → [SP]
001H → PC
1 1110 0000 0001
1E01
INT
None
1
1 1110 100k kkkk
1 1111 kkkk kkkk
1E8k
1Fkk
PAGE k
ADD A,k
K->R5(4:0)
None
1
1
k+A → A
Z,C,DC
8
Segment Data Buffers
The ePVP6800 chip provides a total of 128 bytes data RAM. On the other hand, display Segment
Data Buffers can be stored either in the data RAM of 128 bytes sizes (00h~40h) or in the common
registers of Bank 2 and Bank 3 (20h~3Fh).
a) Data RAM Address
00h~38h
39h~3Eh
3Fh
57X8 Segment Data Buffers
6X8 Key Scanning Data Buffers
SW data register
40h
LED data register
b) Common Registers Address
20
:
Bank0~Bank3
Common registers
(32x8 for each bank)
3F
These buffers store display RAM. The display RAM stores the data transmitted from an external
device to the ePVP6800 through the serial interface and is assigned addresses as follows, in units of 8
bits:
30 of 47 11. 28.2004 (V1.23)
This specification is subject to change without further notice.
ELAN [ ELAN MICROELECTRONICS CORP ]
