ePVP6800
VFD Controller
3、The register initial sets to suggest
The register 0X09 and 0X0C of IOC page 0 & page 1 initial sets suggestion as
follows：0X09 and 0x0C register value = 0B0000xxxx
The register 0x09 and 0X0C of R page 0 & page 1 initial sets suggestion as follows
0X09 and 0x0C register value =0B0000xxxx
7.5 I/O Port
The I/O registers are bi-directional tri-state I/O ports. The I/O ports can be defined as "input" or
"output" pins by the I/O control registers under program control. The I/O data registers and I/O control
registers are both readable and writable. The I/O interface circuit is shown in Fig.6
PCRD
P
R
Q
Q
D
CLK
PCWR
C
L
P
R
PORT
Q
Q
D
IOD
CLK
PDWR
PDRD
C
L
0
1
M
U
X
Fig. 6 The Circuit of I/O Port and I/O Control Register
7.6 RESET
A RESET can be caused by any of the following:
1. Power on reset
2. WDT timeout (if enabled and in GREEN or NORMAL mode)
3. /RESET pin pull low
Once a RESET occurs, the following functions are performed.
ꢁ The oscillator is running, or will be started.
ꢁ The Program Counter (R2) is set to all "0".
ꢁ When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared.
ꢁ The Watchdog timer and prescaler counter are cleared.
ꢁ The Watchdog timer is disabled.
ꢁ The CONT register is set to all "1"
26 of 47 11. 28.2004 (V1.23)
This specification is subject to change without further notice.
ELAN [ ELAN MICROELECTRONICS CORP ]
