ePVP6800
VFD Controller
IOCF bit2=2
And "ENI"
2) Interrupt (jump to Address 8 on (jump to Address 8 (jump to Address 8
Page0)
on Page0)
on Page0)
3) After RETI instruction, jump to
SLEP Next instruction
1) Wake-up
COUNTER3 time out
IOCD bit0=1
Interrupt
Interrupt
2) Interrupt (jump to Address 8 on
Page0)
(jump to Address 8 (jump to Address 8
on Page0)
on Page0)
And "ENI"
3) After RETI instruction, jump to
SLEP Next instruction
1) Wake-up
COUNTER4 time out
IOCD bit1=1
Interrupt
Interrupt
2) Interrupt (jump to Address 8 on
Page0)
(jump to Address 8 (jump to Address 8
on Page0)
on Page0)
And "ENI"
3) After RETI instruction, jump to
SLEP Next instruction
1) Wake-up
COUNTER5 time out
IOCD bit2=1
Interrupt
Interrupt
2) Interrupt (jump to Address 8 on
Page0)
(jump to Address 8 (jump to Address 8
on Page0)
on Page0)
And "ENI"
3) After RETI instruction, jump to
SLEP Next instruction
1) Wake-up
INT1~3
Interrupt
Interrupt
2)Interrupt (jump to Address 8 on
Page0)
IOCF bit4=1 or IOCF
bit5=1 IOCF bit6 = 1
(jump to Address 8 (jump to Address 8
on Page0)
on Page0)
3) after RETI instruction, jump to
SLEP Next instruction
And “ENI
1) Wake-up
IR
Interrupt
Interrupt
2) Interrupt (jump to Address 8 on
Page0)
IOCF bit3= 1
And “ENI
(jump to Address 8 (jump to Address 8
on Page0) on Page0)
3) After RETI instruction, jump to
SLEP Next instruction
NOTES: 1. PORT90 interrupt function is controlled by IOCF Bit 3. It is a falling edge or rising edge trigger
(controlled by CONT register Bit7).
2. PORT9 (1~3) interrupt functions are controlled by IOCF Bits 4, 5, 6). They are falling edge triggers.
7.4 Application notes
1、Call-table instruction:：
Because the call-table instruction can only change the Program Counter's bit7 ~ bit0 at each time,
only 256 addresses can be searched once.
But each program page contains 1024 addresses, if call each 256 addresses as a zone, Then each
page constitutes by four zones.
When a table overlaps two zones, a bug would occur during address searching.
So the member of program must examine the .LST file at any time, the .LST file will jot down the
information that Assembler generated, for example source code, the coding of instruction ,
instruction address, error message etc.
2、Operation requirement for the CPU：
The system frequency must adds a latency time ( 14.33 MHz about 250 ms ；17.91 MHz about
450 ms.). After RA register was setting, it will offer the stable system frequency for the operation
This specification is subject to change without further notice.
11.28.2004 (V123) 25 of 47
ELAN [ ELAN MICROELECTRONICS CORP ]
