ePVP6800
VFD Controller
7.3.3 IOC 5 (PORT5 Switches)
a) Page 1
Bit 7
P57S
R/W-0
Bit 6
P56S
R/W-0
Bit 5
P55S
R/W-0
Bit 4
P54S
R/W-0
Bit 3
Bit 2
Bit 1
Bit 0
Bit 4 ~ Bit 7 (P54S~P57S) : Port5 I/O direction control register
0 ꢂset the relative I/O pin as output HV
1 ꢂset the relative I/O pin into high impedance
7.3.4 IOC 8
a) PAGE 1 (Clock Source and Prescaler for COUNTER1 and COUNTER2)
Bit 7
CNT2S C2_PSC2 C2_PSC1 C2_PSC0 CNT1S C1_PSC2 C1_PSC1 C1_PSC0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 0 ~ Bit 2 (C1_PSC0 ~ C1_PSC2) : COUNTER1 prescaler ratio
C1_PSC2
C1_PSC1
C1_PSC0 COUNTER1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Bit 3 (CNT1S) : COUNTER1 clock source
0 ꢂ16.384kHz
timing = ( 1 /16.384k) * prescaler * (256 – count vaule)
1 ꢂsystem clock
timing = ( 2 / system clock) * prescaler* (256 – count vaule)
This specification is subject to change without further notice.
11.28.2004 (V123) 21 of 47
ELAN [ ELAN MICROELECTRONICS CORP ]
