EM78P5840N/41N/42N
8-Bit Microcontrollers
Bit 4 (INT1):By setting Port 71 to general IO, INT1 will become Port 71 pin’s interrupt
flag. External pull high circuit is needed to trigger an interrupt at Port 71.
If Port 71 has a falling edge trigger signal, the CPU will set this bit. If the
pin is set to /RESET, no interrupt will occur at Port 71 and INT1 register
will be ignored.
"0" : With Interrupt request
"1" : No Interrupt request. Hence no interrupt occurs.
Bit 5 ~ Bit 6 (undefined): These bits are not used
Bit 7 (INT3): External Port 73 pin interrupt flag. If Port 73 has a falling edge trigger
signal (see table below), the CPU will set this bit.
"0" : With Interrupt request
"1" : No Interrupt request. Hence no interrupt occurs.
NOTE
IOCF is the interrupt mask register which can be read from and cleared.
The following shows the trigger edge signals.
Signal
TCC
Trigger
Time out
Counter 1
INT0
Time out
Falling / Rising edge
Falling edge
Falling edge
INT1
INT3
7.2.16 R10~R3F (General Purpose Register)
R10~ R3F (Banks 0 ~ 3)
These are all general purpose registers.
7.3 Special Function Registers
7.3.1 A (Accumulator)
Internal data transfer operation, or instruction operand holding usually involves the
temporary storage function of the Accumulator, which is not an addressable register.
7.3.2 CONT (Control Register)
Bit 7
P70EG
R/W-1
Bit 6
INT
Bit 5
TS
Bit 4
RETBK
R/W-1
Bit 3
PAB
Bit 2
PSR2
R/W-1
Bit 1
PSR1
R/W-1
Bit 0
PSR0
R/W-1
R/W-0
R/W-1
R/W-1
Note: The CONT register is readable (CONTR) and writable (CONTW).
18 •
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
