EM78P5840N/41N/42N
8-Bit Microcontrollers
7.2.11 RA (PLL, Main Clock Selection, Watchdog Timer, DT2H)
Page 0 (PLL Enable Bit, Main Clock Selection Bits, Watchdog Timer Enable Bit)
Bit 7
0
Bit 6
PLLEN
R/W-0
Bit 5
CLK2
R/W-0
Bit 4
CLK1
R/W-0
Bit 3
CLK0
R/W-0
Bit 2
Bit 1
Bit 0
WDTEN
R/W-0
-
-
-
-
R/W-0
Bit 0 (WDTEN): Watchdog control bit
"0" : Disable watchdog
"1" : Enable watchdog
The WDTC instruction can be used to clear the watchdog counter. The
watchdog counter is a free-running on-chip RC oscillator. The WDT will
keep on running even after the oscillator driver has been turned off (i.e.,
in Sleep mode). During normal operation or Sleep mode, a WDT
time-out (if enabled) will cause the device to reset. The WDT can be
enabled or disabled any time during Green mode or Normal mode.
Without the presacler, the WDT time-out period is approximately 18 ms.
Bit 1 ~ Bit 2 (undefined): These bits are not used
Bit 3 ~ Bit 5 (CLK0 ~ CLK2): Main clock selection bits in Crystal mode. These three
bits are NOT used in IRC and ERIC mode.
ꢀ In Crystal Mode:
Different frequencies for the main clock can be chosen with the CLK0,
CLK1 and CLK2 bits. All available clock selections are listed below:
PLLEN
CLK2
CLK1
CLK0
Sub Clock Main Clock
CPU Clock
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
32.768kHz 3.582MHz 3.582MHz (Normal mode
32.768kHz 3.582MHz 3.582MHz (Normal mode
32.768kHz 3.582MHz 3.582MHz (Normal mode
32.768kHz 3.582MHz 3.582MHz (Normal mode
32.768kHz 14.3MHz
32.768kHz 14.3MHz
32.768kHz 14.3MHz
32.768kHz 14.3MHz
14.3MHz (Normal mode)
14.3MHz (Normal mode)
14.3MHz (Normal mode)
14.3MHz (Normal mode)
32.768kHz (Green mode
don’t care don’t care don’t care 32.768kHz don’t care
Bit 6 (PLLEN): PLL's power control bit is the CPU mode control register. This bit is
only used under Crystal mode. Under RC mode, this bit will be
ignored.
"0" : Disable PLL
"1" : Enable PLL
14 •
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)