EM78P5840N/41N/42N
8-Bit Microcontrollers
7.2.14 RE (Interrupt Flag)
Page 0 (Interrupt Flag)
Bit 7
PWM2
R/W-0
Bit 6
0
Bit 5
ADI
Bit 4
PWM1
R/W-0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0 ~ Bit 3 (undefined): Not used. However, these four bits must be cleared to “0” to
prevent possible error.
Bit 4 (PWM1): One PWM1 (Pulse Width Modulation Channel 1) period upon reaching
interrupt flag.
Bit 5 (ADI):
ADC interrupt flag after each sampling
Bit 6 (undefined): This bit must be cleared to “0.” Otherwise, errors may occur.
Bit 7 (PWM2): PWM2 (Pulse Width Modulation Channel 2) interrupt flag
Set when a selected period is reached, reset by software.
7.2.15 RF (Interrupt Status)
Interrupt Status Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INT3
-
-
-
-
INT1
INT0
-
-
CNT1
R/W-0
TCIF
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0 (TCIF): TCC timer overflow interrupt flag. Set when TCC timer overflows.
"0" : With Interrupt request
"1" : No Interrupt request. Hence no interrupt occurs.
Bit 1 (CNT1): Counter1 timer overflow interrupt flag. Set when Counter1 timer
overflows.
"0" : With Interrupt request
"1" : No Interrupt request. Hence no interrupt occurs.
Bit 2 (undefined): This bit is not used
Bit 3 (INT0): By setting Port 70 to general IO, INT0 will become Port 70 pin’s interrupt
flag. If Port 70 has a falling edge/rising edge (controlled by the CONT
register) trigger signal, the CPU will set this bit. If the pin is set to PLLC or
OSCI, no interrupt will occur at Port 70 and INT0 register will be ignored.
"0" : With Interrupt request
"1" : No Interrupt request. Hence no interrupt occurs.
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
