EM78P5840N/41N/42N
8-Bit Microcontrollers
Bit 0 ~ Bit 2 (PSR0 ~ PSR2): TCC/WDT prescaler bits
PSR2
PSR1
PSR0
TCC Ratio
1:2
WDT Ratio
0
0
0
0
0
1
1:1
1:2
1:4
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1:8
1:16
1:32
1:64
1:128
1:256
1:4
1:8
1:16
1:32
1:64
1:128
Bit 3 (PAB): Prescaler assigned bit
"0" : TCC
"1" : WDT
Bit 4 (RETBK): Return the backed-up control value for the interrupt routine
"0" : Disable
"1" : Enable
When this bit is set to “1”, the CPU will store ACC, R3 status, and R5
PAGE automatically after an interrupt is triggered. This bit will be restored
after the RETI instruction. When this bit is set to “0”, user needs to store
ACC, R3 status, and R5 PAGE in the program.
Bit 5 (TS): TCC signal source
"0" : Internal instruction clock cycle
"1" : IRC output
Bit 6 (INT): INT enable flag
"0" : Interrupt masked by DISI or hardware interrupt
"1" : Interrupt enabled by ENI/RETI instructions
Bit 7 (P70EG): If Port 70 is set to INT0 input, P70EG can select the interrupt toggle
type.
"0" : P70 's interrupt source is a rising edge signal and falling edge signal
"1" : P70 's interrupt source is a falling edge signal
TCC and WDT
An 8-bit counter is available as the prescaler for the TCC or WDT. The prescaler is
available for either TCC or WDT at a time. Availability of the 8-bit counter for TCC or
WDT is contingent on the status of Bit 3 (PAB) of the CONT register as shown above.
See the prescaler ratio for TCC/WDT in the table above. Figure 6-3 below depicts the
block diagram of TCC/WDT.
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
