EM78P5840N/41N/42N
8-Bit Microcontrollers
If PPL is enabled, CPU will operate in Normal mode (high frequency).
Otherwise, it will run in Green mode (low frequency, 32768 Hz).
3.58MHz, 14.3MHz
CLK2 ~ CLK0
PLL circuit
1
switch
System clock
0
ENPLL
Sub-clock
32.768kHz
Figure 6-2 Correlation between 32.768kHz and PLL
Bit 7 (undefined): This bit is not used. However, always keep this bit at “0” to preclude
possible error.
When Bit 7and Bit 6 are set to “0” and are included in the SLEP instruction,
the following table shows the status after wake up and the wake-up sources.
Wake-up Signal
Sleep Mode
RA(7,6)=(0,0)
+ SLEP
-
TCC time out
IOCF Bit 0 =1
No effect
No effect
Counter 1 time out
IOCF Bit 1=1
WDT time out
Reset and jump to Address 0
Reset and Jump to Address 0
Port 7 (0, 1, 3)*
* Port 70 wake-up function is controlled by IOCF Bit 3. It is a falling edge or
rising edge trigger (controlled by CONT register Bit 7).
Port 71 wake-up function is controlled by IOCF Bit 4. It is a falling edge
trigger.
Port 73 wake-up function is controlled by IOCF Bit 7. It is a falling edge
trigger.
Page 3 DT2H: Most Significant Bit (Bit 1 ~ Bit 0) of PWM2 Duty Cycle
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
PWM2[9] PWM2[8]
R/W-0 R/W-0
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
Bit 0 ~ Bit 1 (PWM2[8] ~ PWM2[9]): Most Significant bit of PWM2 Duty Cycle
A specified value keeps the PWM2 output to remain high until the it
matches with the value of TMR2.
Bit 2 ~ Bit 7 (undefined): These bits are not used
Product Specification (V1.0) 04.25.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
