EM78P458/459
OTP ROM
4.3 TCC/WDT & Prescaler
An 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is available for either the
TCC or WDT only at any given time, and the PAB bit of CONT register is used to determine the
prescaler assignment. The PSR0~PSR2 bits determine the prescale ratio. The prescaler is cleared
each time the instruction is written to TCC under TCC mode. The WDT and prescaler, when assigned to
WDT mode, are cleared by the WDTC or SLEP instructions. Fig. 5 depicts the circuit diagram of
TCC/WDT.
• R1(TCC) is an 8-bit timer/counter. The TCC clock source can be internal or external clock input (edge
selectable from TCC pin). If TCC signal source is from internal clock, TCC will increase by 1 at every
instruction cycle (without prescaler). Referring to Fig. 5, selection of CLK=Fosc/2 or CLK=Fosc/4
depends on the CODE Option bit CLKS. CLK=Fosc/2 if CLKS bit is "0", and CLK=Fosc/4 if CLKS bit is
"1".
• If TCC signal source is from external clock input, TCC will increase by 1 at every falling edge or rising
edge of TCC pin.
• The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even after
the oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a
WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled at any
time during the normal mode by software programming. Refer to WDTE bit of IOCE0 register. Without
presacler, the WDT time-out period is approximately 18 ms1.
1 NOTE: VDD=5V,Setup time period = 18ms ± 30%.
VDD=3V,Setup time period = 22ms ± 30%.
This specification is subject to change without prior notice.
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06.25.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
