EM78P458/459
OTP ROM
PCRD
P
R
Q
D
CLK
PCWR
_
Q
C
L
P60 ~ P67
PORT
P
R
IOD
Q
D
CLK
_
Q
PDWR
C
L
M
U
X
0
1
PDRD
TI n
P
R
D
Q
CLK
_
Q
C
L
NOTE: Pull-high (down) and Open-drain are not shown in the figure.
Fig. 8 The Circuit of I/O Port and I/O Control Register for P60~P67
IOCE.1
P
Q
D
R
CLK
Interrupt
_
Q
C
L
RE.1
ENI Instruction
P
T10
T11
D
Q
R
P
CLK
Q
D
R
_
Q
C
CLK
L
_
Q
C
L
T17
DISI Instruction
Interrupt
(Wake-up from SLEEP)
/SLEP
Next Instruction
(Wake-up from SLEEP)
Fig. 9 Block Diagram of Port 6 with Input Changed Interrupt/Wake-up
This specification is subject to change without prior notice.
25
06.25.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
