EM78P458/459
OTP ROM
14. IOC81 ( PRD1: Period of PWM1 ):
The content of IOC81 is a period (time base) of PWM1. The frequency of PWM1 is the reverse of the
period.
15. IOC91 ( DT2L: the Least Significant Byte ( Bit 7 ~ Bit 0 ) of Duty Cycle of
PWM2 )
A specified value keeps the of PWM1 output to stay at high until the value matches with TMR2.
16. IOCA1 ( DT2H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle of
PWM2 )
7
6
5
4
3
2
-
1
0
CALI2
SIGN2
VOF2[2]
VOF2[1]
VOF2[0]
PWM2[9] PWM2[8]
• Bit 7 (CALI2): Calibration enable bit
0 = Calibration disable;
1 = Calibration enable.
• Bit 6 (SIGN2): Polarity bit of offset voltage
0 = Negative voltage;
1 = Positive voltage.
• Bit 5:Bit 3 (VOF2[2]:VOF2[0]): Offset voltage bits
• Bit 1:Bit 0 (PWM2[9]:PWM2[8]): The Most Significant Byte of PWM1 Duty Cycle
A specified value keeps the PWM2 output to stay at high until the value matches with TMR2.
17. IOCB1 ( PRD2: Period of PWM2 )
The content of IOCB1 is a period (time base) of PWM2. The frequency of PWM2 is the reverse of the
period.
18. IOCC1 ( DL1L: the Least Significant Byte ( Bit 7 ~ Bit 0 ) of Duty Cycle Latch of
PWM1 )
The content of IOCC1 is read-only.
19. IOCD1 ( DL1H: the Most Significant Byte ( Bit 1 ~ Bit 0 ) of Duty Cycle Latch of
PWM1 )
The content of IOCD1 is read-only.
20. IOCE1 ( DL2L: the Least Significant Byte ( Bit 7 ~ Bit 0) of Duty Cycle Latch of
PWM2 )
This specification is subject to change without prior notice.
20
06.25.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
