EM78P458/459
OTP ROM
10. IOCF0 (Interrupt Mask Register)
7
-
6
5
4
3
2
1
ICIE
0
CMPIE
PWM2IE
PWM1IE
ADIE
EXIE
TCIE
• Bit 7: Unimplemented, read as ‘0’.
Individual interrupt is enabled by setting its associated control bit in the IOCF0 to "1".
Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig.
11.
• Bit 6 (CMPIE) CMPIF interrupt enable bit.
0: disable CMPIF interrupt
1: enable CMPIF interrupt
• Bit 5 (PWM2IE) PWM2IF interrupt enable bit.
0: disable PWM2 interrupt
1: enable PWM2 interrupt
• Bit 4 (PWM1IE) PWM1IF interrupt enable bit.
0: disable PWM1 interrupt
1: enable PWM1 interrupt
• Bit 3 (ADIE) ADIF interrupt enable bit.
0: disable ADIF interrupt
1: enable ADIF interrupt
• Bit 2 (EXIE) EXIF interrupt enable bit.
0: disable EXIF interrupt
1: enable EXIF interrupt
• Bit 1 (ICIE) ICIF interrupt enable bit.
0: disable ICIF interrupt
1: enable ICIF interrupt
• Bit 0 (TCIE) TCIF interrupt enable bit.
0: disable TCIF interrupt
1: enable TCIF interrupt
IOCF0 register is both readable and writable.
11. IOC51 ( PWMCON ):
7
6
5
4
3
2
1
0
PWM2E
PWM1E
T2EN
T1EN
T2P1
T2P0
T1P1
T1P0
• Bit 7 (PWM2E): PWM2 enable bit
0 = PWM2 is off (default value), and its related pin carries out the P52 function.
1 = PWM2 is on, and its related pin will be set to output automatically.
This specification is subject to change without prior notice.
18
06.25.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
