EM78P458/459
OTP ROM
PCRD
Q
D
D
CLK
PCWR
_
Q
C
L
P
R
PORT
IOD
Q
CLK
PDWR
_
Q
C
L
PDRD
M
U
X
0
1
NOTE: Pull-down is not shown in the figure.
Fig. 6 The Ccircuit of I/O Port and I/O Control Register for Port 5
PCRD
P
R
Q
D
CLK
PCWR
_
Q
C
L
P50, /INT
PORT
P
R
Q
D
IOD
CLK
_
Q
PDWR
C
L
Bit 6 of IOCE0
M
U
X
0
1
P
R
D
Q
CLK
_
Q
C
L
PDRD
TI 0
P
R
D
Q
CLK
_
Q
C
L
INT
NOTE: Pull-high (down) and Open-drain are not shown in the figure.
Fig. 7 The Circuit of I/O Port and I/O Control Register for P50(/INT)
This specification is subject to change without prior notice.
24
06.25.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
