EM78P417N/418N/419N
8-Bit Microprocessor with OTP ROM
6 Function Description
6.1 Operational Registers
6.1.1 R0 (Indirect Address Register)
R0 is not a physically implemented register. Its major function is to perform as an
indirect address pointer. Any instruction using R0 as a pointer, actually accesses the
data pointed by the RAM Select Register (R4).
6.1.2 R1 (Time Clock /Counter)
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Increased by an external signal edge through the TCC pin, or by the instruction
cycle clock.
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External signal of TCC trigger pulse width must be greater than one instruction.
The signals to increase the counter are determined by Bit 4 and Bit 5 of the CONT
register.
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Writable and readable as any other registers.
6.1.3 R2 (Program Counter) and Stack
R 3
R eset V ector
Interrupt V ector
000H
008H
A11 A10
A9
~
A0
C ALL
R ET
R ET L
R ET I
00 P A G E 0 0000~03FF
01 P A G E 0400~07FF
Stack Level 1
Stack Level 2
Stack Level 3
Stack Level 4
Stack Level 5
Stack Level 6
Stack Level 7
Stack Level 8
O n-chip Prog ram
M em o ry
1
10 P A G E 2 0800~0B FF
11 P A G E 3 0C 00~0FFF
FFFH
Fig. 6-1 Program Counter Organization
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R2 and hardware stacks are 12-bit wide. The structure is depicted in the table
under Section 6.1.3.1 Data Memory Configuration (next section).
Generates 4K×13 bits on-chip ROM addresses to the relative programming
instruction codes. One program page is 1024 words long.
The contents of R2 are all set to "0"s when a RESET condition occurs.
8 •
Product Specification (V1.0) 06.23.2005
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
