EM78P350N
8-Bit Microprocessor with OTP ROM
6.2.7 IOCF (Interrupt Mask Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWM3IE PWM2IE PWM1IE
ADIE
EXIE1
EXIE0
ICIE
TCIE
NOTE
■ IOCF register is both readable and writable
■ Individual interrupt is enabled by setting its associated control bit in the IOCF to "1."
■ Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction. Refer to Fig. 6-8 (Interrupt Input Circuit) under Section 6.6 (Interrupt).
Bit 7 (PWM3IE): PWM3IF interrupt enable bit
0 = Disable PWM3 interrupt
1 = Enable PWM3 interrupt
Bit 6 (PWM2IE): PWM2IF interrupt enable bit
0 = Disable PWM2 interrupt
1 = Enable PWM2 interrupt
Bit 5 (PWM1IE): PWM1IF interrupt enable bit
0 = Disable PWM1 interrupt
1 = Enable PWM1 interrupt
Bit 4 (ADIE):
ADIF interrupt enable bit
0 = Disable ADIF interrupt
1 = Enable ADIF interrupt
When the ADC Complete status is used to enter an interrupt vector
or to enter next instruction, the ADIE bit must be set to “Enable.“
Bit 3 (EXIE1):
Bit 2 (EXIE0):
Bit 1 (ICIE):
EXIF External 1 interrupt enable bit
0 = Disable EXIF interrupt
1 = Enable EXIF interrupt
EXIF External 0 interrupt enable bit
0 = Disable EXIF interrupt
1 = Enable EXIF interrupt
ICIF interrupt enable bit
0 = Disable ICIF interrupt
1 = Enable ICIF interrupt
If Port 6 Input Status Change Interrupt is used to enter an interrupt
vector or to enter next instruction, the ICIE bit must be set to
“Enable“.
Bit 0 (TCIE):
TCIF interrupt enable bit.
0 = Disable TCIF interrupt
1 = Enable TCIF interrupt
32 •
Product Specification (V1.0) 09.14.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
