EM78P350N
8-Bit Microprocessor with OTP ROM
Bit 1~Bit 0 (TM4P): Timer4 Prescaler bit
TM4P1
TM4P0
Prescaler Rate
1:1
0
0
0
1
1
1
0
1
1:4
1:8
1:16
6.2.5 IOCA (TCMPCON: Comparator Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
“0”
“0”
“0”
CMPIF
CMPIE
CPOUT
COS1
COS0
Bits 7~ 5:
Unimplemented, read as ‘0’
Bit 4 (CMPIF): Comparator interrupt flag. Set when a change occurs in the output of
Comparator. Reset by software.
Bit 3 (CMPIE): CMPIF interrupt enable bit
0 = Disable CMPIF interrupt
1 = Enable CMPIF interrupt
When the Comparator output status change is used to enter interrupt
vector or to enter next instruction, the CMPIE bit must be set to “Enable“.
Bit 2 (CPOUT): the result of the comparator output
Bit 1 ~ Bit 0 (COS1 ~ COS0): Comparator/OP Select bits
COS1 COS0
Function Description
The Comparator and OP arenot used. P56 functions as
normal I/O pin
0
0
0
1
Functions as Comparator and P56 functions as normal
I/O pin
Functions as Comparator and P56 functions as
Comparator output pin (CO)
1
1
0
1
Functions as OP and P56 functions as OP output pin (CO)
6.2.6 IOCE (WDT Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WDTE
EIS0
EIS1
PSWE
PSW2
PSW1
PSW0
LVDIE
Bit 7 (WDTE): Control bit used to enable the Watchdog Timer
0 = Disable WDT
1 = Enable WDT
WDTE is both readable and writable.
Bit 6 (EIS0): Control bit used to define the function of the P52 (/INT0) pin
0 = P52, normal I/O pin
1 = /INT0, external interrupt pin. In this case, the I/O control bit of P52
(Bit 2 of IOC50) must be set to "1", and tied to a pull-high register (75 KΩ)
30 •
Product Specification (V1.0) 09.14.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
