EM78P350N
8-Bit Microprocessor with OTP ROM
NOTE
■ When EIS0 is "0," the path of /INT0 is masked. When EIS0 is "1," the status of /INT0
pin can also be read by way of reading Port 5 (R5). Refer to Fig. 6-4 (I/O Port and I/O
Control Register Circuit for P52 (/INT0)) under Section 6.4 (I/O Ports).
■ EIS0 is both readable and writable.
Bit 5 (EIS1): Control bit used to define the function of the P53 (/INT1) pin
0 = P53, normal I/O pin
1 = /INT1, external interrupt pin. In this case, the I/O control bit of P53 (Bit 3
of IOC50) must be set to "1", and tied to a pull-high register (75 KΩ).
NOTE
■ When EIS1 is "0," the path of /INT1 is masked. When EIS1 is "1," the status of /INT1
pin can also be read by way of reading Port 5 (R5). Refer to Fig. 6-4 (I/O Port and I/O
Control Register Circuit for P53 (/INT1)) under Section 6.4 (I/O Ports).
■ EIS1 is both readable and writable.
Bit 4 (PSWE): Prescaler enable bit for WDT
0 = prescaler disable bit. WDT rate is 1:1
1 = prescaler enable bit. WDT rate is set as Bit 4~Bit 2
Bit 3 ~ Bit 1 (PSW2 ~ PSW0): WDT prescaler bits.
PSW2
PSW1
PSW0
WDT Rate
1:2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Bit 0 (LVDIE) LVDIF interrupt enable bit.
0 = disable LVDIF interrupt
1 = enable LVDIF interrupt
Product Specification (V 1.0) 09.14.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
