EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
Binary Instruction Hex
Mnemonic
Operation
A & R → A
A & R → R
A ⊕ R → A
A ⊕ R → R
A + R → A
A + R → R
R → A
R → R
/R → A
/R → R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1), R(0) → C,
C → A(7)
R(n) → R(n-1), R(0) → C,
C → R(7)
R(n) → A(n+1), R(7) → C,
C → A(0)
R(n) → R(n+1), R(7) → C,
C → R(0)
Status Affected
0 0010 10rr rrrr
0 0010 11rr rrrr
0 0011 00rr rrrr
0 0011 01rr rrrr
0 0011 10rr rrrr
0 0011 11rr rrrr
0 0100 00rr rrrr
0 0100 01rr rrrr
0 0100 10rr rrrr
0 0100 11rr rrrr
0 0101 00rr rrrr
0 0101 01rr rrrr
0 0101 10rr rrrr
0 0101 11rr rrrr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
AND A,R
AND R,A
XOR A,R
XOR R,A
ADD A,R
ADD R,A
MOV A,R
MOV R,R
COMA R
COM R
Z
Z
Z
Z
Z, C, DC
Z, C, DC
Z
Z
Z
Z
INCA R
Z
INC R
Z
DJZA R
DJZ R
None
None
0 0110 00rr rrrr
0 0110 01rr rrrr
0 0110 10rr rrrr
0 0110 11rr rrrr
0 0111 00rr rrrr
06rr
06rr
06rr
06rr
07rr
RRCA R
RRC R
C
C
RLCA R
RLC R
C
C
R(0-3) → A(4-7),
R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
R+1 → R, skip if zero
0 → R(b)
SWAPA R
None
0 0111 01rr rrrr
0 0111 10rr rrrr
0 0111 11rr rrrr
0 100b bbrr rrrr
0 101b bbrr rrrr
0 110b bbrr rrrr
0 111b bbrr rrrr
07rr
07rr
07rr
0xxx
0xxx
0xxx
0xxx
SWAP R
JZA R
None
None
None
None 2
None 3
None
None
JZ R
BC R,b
BS R,b
JBC R,b
JBS R,b
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP], (Page, k) →
PC
1 00kk kkkk kkkk 1kkk
CALL k
None
1 01kk kkkk kkkk 1kkk
1 1000 kkkk kkkk 18kk
1 1001 kkkk kkkk 19kk
1 1010 kkkk kkkk 1Akk
1 1011 kkkk kkkk 1Bkk
JMP k
(Page, k) → PC
k → A
A ∨ k → A
A & k → A
A ⊕ k → A
None
None
Z
MOV A,k
OR A,k
AND A,k
XOR A,k
Z
Z
1 1100 kkkk kkkk 1Ckk RETL k
1 1101 kkkk kkkk 1Dkk SUB A,k
k → A, [Top of Stack] → PC
k-A → A
None
Z, C, DC
1 1110 1000 kkkk
1EAK LCALL k
k kkkk kkkk kkkk
PC+1→[SP], k→PC
None
1 1110 1000 kkkk
1EBK LJMP k
k kkkk kkkk kkkk
k→PC
None
1 1111 kkkk kkkk 1Fkk
1
ADD A,k
k+A → A
Z, C, DC
Note: This instruction is applicable to IOC50~IOCF0, IOC51 ~ IOCF1 only.
2
This instruction is not recommended for RF operation.
3
This instruction cannot operate under RF.
82 •
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
