EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.15 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one
or more operands. Normally, all instructions are executed within one single instruction
cycle (one instruction consists of two oscillator periods), unless the program counter is
changed by instructions "MOV R2,A," "ADD R2,A," or by instructions of arithmetic or
logic operation on R2 (e.g., "SUB R2,A," "BS(C) R2,6," "CLR R2," etc.). In this case,
these instructions need one or two instruction cycles as determined by the Code Option
Register CYES bit.
In addition, the instruction set has the following features:
1. Every bit of any register can be set, cleared, or tested directly.
2. The I/O registers can be regarded as general registers. That is, the same
instruction can operate on I/O registers.
The following symbols are used in the Instruction Set table:
Convention:
R = Register designator that specifies which one of the registers (including operation and general purpose
registers) is to be utilized by the instruction.
Bits 6 and 7 in R4 determine the selected register bank.
b = Bit field designator that selects the value for the bit located in the register R and which affects the
operation.
k = 8 or 10-bit constant or literal value
Binary Instruction Hex
Mnemonic
Operation
No Operation
Status Affected
0 0000 0000 0000 0000
0 0000 0000 0001 0001
0 0000 0000 0010 0002
0 0000 0000 0011 0003
0 0000 0000 0100 0004
0 0000 0000 rrrr 000r
0 0000 0001 0000 0010
0 0000 0001 0001 0011
0 0000 0001 0010 0012
NOP
None
C
DAA
Decimal Adjust A
CONTW
SLEP
WDTC
IOW R
ENI
A → CONT
0 → WDT, Stop oscillator
0 → WDT
None
T, P
T, P
A → IOCR
None1
None
None
None
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC,
Enable Interrupt
CONT → A
DISI
RET
0 0000 0001 0011 0013
RETI
None
0 0000 0001 0100 0014
0 0000 0001 rrrr 001r
CONTR
IOR R
None
IOCR → A
None1
0 0000 01rr rrrr
00rr
MOV R,A
CLRA
A → R
0 → A
None
0 0000 1000 0000 0080
Z
0 0000 11rr rrrr
0 0001 00rr rrrr
0 0001 01rr rrrr
0 0001 10rr rrrr
0 0001 11rr rrrr
0 0010 00rr rrrr
0 0010 01rr rrrr
00rr
01rr
01rr
01rr
01rr
02rr
02rr
CLR R
0 → R
R-A → A
R-A → R
R-1 → A
R-1 → R
A ∨ VR → A
A ∨ VR → R
Z
SUB A,R
SUB R,A
DECA R
DEC R
Z, C, DC
Z, C, DC
Z
Z
Z
Z
OR A,R
OR R,A
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
