EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
6.2.6 IOCA0 (IR and TCCC Scale Control Register)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TCCCSE TCCCS2 TCCCS1 TCCCS0
IRE
HF
LGP
IROUTE
Bit 7 (TCCCSE): Scale enable bit for TCCC
An 8-bit counter is provided as scale for TCCC and IR-Mode. When
in IR-Mode, TCCC counter scale uses the low-time segments of the
pulse generated by Fcarrier frequency modulation (see Fig. 6-11 in
Section 6.8.2, Function Description).
0 = scale disable bit, TCCC rate is 1:1
1 = scale enable bit, TCCC rate is set as Bit 6 ~ Bit 4
Bit 6 ~ Bit 4 (TCCCS2 ~ TCCCS0): TCCC scale bits
The TCCCS2 ~ TCCCS0 bits of the IOCA0 register are used to
determine the scale ratio of TCCC as shown below:
TCCCS2
TCCCS1
TCCCS0
TCCC Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Bit 3 (IRE):
Infrared Remote Enable bit
0 = Disable IRE, i.e., disable H/W Modulator Function. The IROUT
pin is fixed at a high level and the TCCC is an Up Counter.
1 = Enable IRE, i.e., enable H/W Modulator Function. Pin 67 is
defined as IROUT. If HP=1, the TCCC counter scale uses the
low-time segments of the pulse generated by the Fcarrier
frequency modulation (see Fig. 6-11 in Section 6.8.2, Function
Description). When HP=0, the TCCC is an Up Counter.
Bit 2 (HF):
High Frequency bit
0 = PWM application. IROUT waveform is achieved base on the
high-pulse width timer and low-pulse width timer which
determine the high time width and low time width respectively.
1 = IR application mode. The low-time segments of the pulse
generated by the Fcarrier frequency modulation (see Fig. 6-11 in
Section 6.8.2, Function Description)
Bit 1 (LGP):
Long Pulse.
0 = The high-time and low-time registers are valid
1 = The high-time register is ignored. A single pulse is generated.
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
