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EM78P341 参数 Datasheet PDF下载

EM78P341图片预览
型号: EM78P341
PDF下载: 下载PDF文件 查看货源
内容描述: 8位OTP微 [8-Bit Microprocessor with OTP ROM]
分类和应用: OTP只读存储器
文件页数/大小: 102 页 / 1294 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM78P341N/342N/343N  
8-Bit Microprocessor with OTP ROM  
Bit 2 (CMPWE): Comparator wake-up enable bit  
0 = Disable Comparator wake-up  
1 = Enable Comparator wake-up  
When Comparator enters sleep mode, this bit must be set to “Enable“.  
Port 5 input change to wake-up status enable bit  
Bit 1 (ICWE):  
0 = Disable Port 5 input change to wake-up status  
1 = Enable Port 5 input change to wake-up status  
When Port 5 change enters sleep mode, this bit must be set to “Enable“.  
Bit 0 (LVDWE): Low Voltage Detect wake-up enable bit  
0 = Disable Low Voltage Detect wake-up  
1 = Enable Low Voltage Detect wake-up  
When the Low Voltage Detect is used to enter an interrupt vector or to  
wake-up the IC from sleep with Low Voltage Detect running, the  
LVDWE bit must be set to “Enable“.  
6.1.15 RF (Interrupt Status 2 Register)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
LPWTIF  
HPWTIF  
TCCCIF  
TCCBIF  
TCCAIF  
EXIF  
ICIF  
TCIF  
NOTE  
“1” means there is interrupt request; “0” means no interrupt occurs  
RF can be cleared by instruction but cannot be set.  
IOCF0 is the relative interrupt mask register.  
Reading RF will result to "logic AND" of RF and IOCF0.  
Bit 7 (LPWTIF): Internal low-pulse width timer underflow interrupt flag for IR/PWM  
function. Reset by software.  
Bit 6 (HPWTIF): Internal high-pulse width timer underflow interrupt flag for IR/PWM  
function. Reset by software.  
Bit 5 (TCCCIF): TCCC overflow interrupt flag. Set when TCCC overflows. Reset by  
software.  
Bit 4 (TCCBIF): TCCB overflow interrupt flag. Set when TCCC overflows. Reset by  
software.  
Bit 3 (TCCAIF): TCCA overflow interrupt flag. Set when TCCC overflows. Reset by  
software.  
Bit 2 (EXIF):  
Bit 1 (ICIF):  
Bit 0 (TCIF):  
External interrupt flag. Set by falling edge on /INT pin. Reset by  
software.  
Port 5 input status change interrupt flag. Set when Port 5 input  
changes. Reset by software.  
TCC overflow interrupt flag. Set when TCC overflows. Reset by  
software.  
6.1.16 R10 ~ R3F  
All of these are 8-bit general-purpose registers.  
Product Specification (V1.0) 12.01.2006  
(This specification is subject to change without further notice)  
17  
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