EM78P341N/342N/343N
8-Bit Microprocessor with OTP ROM
NOTE
■ The IOCF0 register is both readable and writable.
■ Individual interrupt is enabled by setting its associated control bit in the IOCF0 and in
IOCE0 Bit 4 & 5 to "1".
■ Global interrupt is enabled by the ENI instruction and is disabled by the DISI
instruction. Refer to Fig. 6-7 (Interrupt Input Circuit) under Section 6.6 (Interrupt).
Bit 7 (LPWTIE): LPWTIF interrupt enable bit
0 = Disable LPWTIF interrupt
1 = Enable LPWTIF interrupt
Bit 6 (HPWTIE): HPWTIF interrupt enable bit
0 = Disable HPWTIF interrupt
1 = Enable HPWTIF interrupt
Bit 5 (TCCCIE): TCCCIF interrupt enable bit
0 = Disable TCCCIF interrupt
1 = Enable TCCCIF interrupt
Bit 4 (TCCBIE): TCCBIF interrupt enable bit
0 = Disable TCCBIF interrupt
1 = Enable TCCBIF interrupt
Bit 3 (TCCAIE): TCCAIF interrupt enable bit
0 = Disable TCCAIF interrupt
1 = Enable TCCAIF interrupt
Bit 2 (EXIE):
Bit 1 (ICIE):
Bit 0 (TCIE):
EXIF interrupt enable bit
0 = Disable EXIF interrupt
1 = Enable EXIF interrupt
ICIF interrupt enable bit
0 = Disable ICIF interrupt
1 = Enable ICIF interrupt
TCIF interrupt enable bit.
0 = Disable TCIF interrupt
1 = Enable TCIF interrupt
6.2.12 IOC51 (TCCA Counter)
IOC51 (TCCA) is an 8-bit clock counter. It can be read, written, and cleared on any
reset condition and is an Up Counter.
NOTE
■ TCCA timeout period [1/Fosc x (256-TCCA cnt) x 1(CLK=2)]
■ TCCA timeout period [1/Fosc x (256-TCCA cnt) x 2 (CLK=4)]
Product Specification (V1.0) 12.01.2006
(This specification is subject to change without further notice)
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ELAN [ ELAN MICROELECTRONICS CORP ]
