EM78P257
OTP ROM
LSB Counter
MSB Counter
IRE
Loadedbysoftwarewiththenumberofpulsesrequiredinapulseburst;loading’ 0’ isnot
allowed.
Infrared Remote Enable bit
IR OUT
IR output port.IIROUT = 20mA, when the output voltage drops to 2.4V, at Vdd = 5V
2.1 Operation of the Hardware Modulator
1. Enable IRE , set parameter for IR (RD )
2. Load Low-time register (IOC91)
3. Load High-time register (IOCA1)
4. Load MSB and LSB Counter register (IOC61, IOC71)
The Low-time, High-time, MSB Counter, and LSB Counter register are loaded by software. The
following instructions is an example for generating five pulses train:
MOV A,@0B00001000
MOV 0x0D,A
MOV A, @0x10
IOW 0x08
;(Enable IR)
;(Enable TCCBH)
BS 0x03,6
;(Select control register segment 1)
MOV A,@0x10
IOW 0x09
;(Set Low-Time Register=10h)
MOV A,@0x20
IOW 0x0A
MOV A,@0x5
IOW 0x06
;(Set High-Time Register=20h)
;(Set pulse number = 5 => LSB=5, MSB=0)
;LSB=5
MOV A,@0x00
IOW 0x07
;MSB=0
As soon as the LSB Counter Register is loaded, the Hardware Modulator is started and IR OUT
becomes active (LOW). Simultaneously, the contents of the Low-time register are loaded into the
Pulse Timer, which is then decremented by ‘ 1’ every oscillator clock cycle. When the value held in
the Pulse Timer becomes zero the contents of the LSB & MSB Counter are decremented by ‘ 1’ and
IR OUT become inactive (HIGH).
The contents of the High-time register are now loaded into the Pulse Timer which is decremented
by ‘ 1’ every oscillator clock cycle. When the value held in the Pulse Timer becomes zero, IR OUT
becomes active (LOW). One pulse cycle has now been generated.
The process of alternately loading the contents of the Low-time register and High-time register into
the Pulse Timer continues until the contents of the LSB & MSB Counter become zero. When this
occurs TCCBIF is asserted; an interrupt to the CPU is generated and the interrupt flag is raised
stopping the operation of the Hardware Modulator (If TCCBIF want to be clear ,the IR must be
disable firstly). The programmed pulse train has now been generated. If the Hardware Modulator
This specification is subject to change without prior notice.
61
07.27.2004 (V1.4)