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EM78P257B 参数 Datasheet PDF下载

EM78P257B图片预览
型号: EM78P257B
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器 [8-BIT MICROCONTROLLER]
分类和应用: 微控制器
文件页数/大小: 91 页 / 1917 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM78P257  
OTP ROM  
1st  
CLK  
2nd  
CLK  
11th  
10th  
CLK  
CLK  
CLK  
Tpi  
Tsci  
Tsca  
Tsdc  
Tsdc  
DATA  
Parity Bit Stop bit  
Start bit  
Bit0~Bit7  
If CLK is low (inhibit status), no data transmission occurs.  
If CLK is high and DATA is low (request-to-send), data is updated. Data is received from the system  
and no transmission is started by EM78A/B until CLK and DATA are both high. IF CLK and DATA  
are both high, the transmission is ready. DATA is valid prior to the falling edge of CLK and beyond  
the rising edge of CLK. During transmission, EM78P257A/B check for line contention by checking  
for an inactive level on CLK at interval not to exceed 100u seconds. Contention occurs when the  
system lowers CLK to inhibit EM78P257A/B output after EM78P257A/B has started a transmission.  
If this occurs before the rising edge of the tenth clock, EM78P257A/B internally stores its buffer and  
returns DATA and CLK to an active level. If the contention does not occur by the tenth clock, the  
transmission is completed.  
Following a transmission, the system inhibits EM78P257A/B by holding CLK low until it can service  
the input or until the system receives a request to send a response from EM78P257A/B.  
(3) Receiving DATA (from system to EM78P257A/B)  
Inhibit  
2nd  
9th  
10th  
CLK  
1st  
CLK  
11th  
CLK  
CLK  
CLK  
CLK  
Tmca  
Tmdc  
Tmci  
DATA  
Bit0~Bit7  
Parity Bit Stop bit Line Control Bit  
Start bit  
System first checks if EM78P257A/B is transmitting data. If transmitting, the system can override  
the output by forcing CLK to an inactive level prior to the tenth clock. If EM78P257A/B transmission  
is beyond the tenth clock, the system receives the data. If EM78P257A/B is not transmitting or if the  
system choose to override the output, the system forces CLK to an inactive level for a period of not  
less than 100us while preparing for output. When the system is ready to output start bit (0), it allows  
CLK to go to active level. If request-to-send is detected, EM78P257A/B clocks 11 bits. Following  
the tenth clock, EM78P257A/B checks for an active level on the DATA line, and if found, forces  
This specification is subject to change without prior notice.  
57  
07.27.2004 (V1.4)  
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