EM78P257
OTP ROM
• The decimal value of its contents determines the number of oscillator cycles indicating that the IR
OUT pin is active. The inactive period of IR OUT can be calculated as follow:
tHigh=(decimal value held in High-time register)/fosco
• Pulse timer Register :The contents of the Low-time and High-time registers which are loaded
alternately into the Pulse timer. When loaded, the Pulse timer contents are decremented by “ 1” every
oscillator cycle. Upon reaching zero, the Pulse timer will be loaded with the contents of the other
register.
Table 29 TCCX Status Register (2)
7
-
6
5
4
3
-
2
1
0
TCCBIE
TCCBTS
TCCBTE
TCCCIE
TCCCTS
TCCCTE
• Bit 6(TCCBIE) TCCBIF interrupt enable bit.
0: disable TCCBIF interrupt
1: enable TCCBIF interrupt
Table 30 TCCX Control Register
7
6
5
4
3
-
2
-
1
-
0
-
TCC2E
TCC4E
TCC6E
TCCBE
• Bit 4 (TCCBE): Control bit which is used to enable most significant byte of counter
1 = Enable most significant byte of TCCBH.
0 = Disable most significant byte of TCCBH (default value).
Table 31 IR Control Register
7
6
5
4
3
2
1
0
DP1
DP0
MF1
MF0
IRE
HF
LGP
PWM
• Bit7:Bit6 (DP1:DP0) : Duty and Period ratio
DP1
DP0
Ratio
0
0
1
1
0
1
0
1
1:2(default)
1:3
1:4
-
• Bit 5:Bit 4 ( MF1:MF0 ) : Modulated frequency
MF1
MF0
Fosco
Fosc/1
-
0
0
1
1
0
1
0
1
Fosc/4
Fosc/8
• Bit 3(IRE) Infrared Remote Enable bit
0: Disable IRE. Disable H/W Modulator Function.
This specification is subject to change without prior notice.
63
07.27.2004 (V1.4)
ELAN [ ELAN MICROELECTRONICS CORP ]
