EM78815
8-Bit Microcontroller
Bit 1 ~ Bit 2 (KT0 ~ KT1) : Keytone output frequency and its power control
KT1
0
KT0
0
Keytone Frequency and Power
32.768kHz/32 = 1.024kHz clock and enable
32.768kHz/16 = 2.048kHz clock and enable
32.768kHz/8 = 4.096kHz clock and enable
Power-off keytone
0
1
1
0
1
1
Bit 3 (URINV) : Enable UART TXD, RXD port inverse output
0 → Disable UART TXD, RXD port inverse output
1 → Enable UART TXD, RXD port inverse output
Bit 4 ~ Bit 5 (DA0~DA1) : These two bits are the least significant bits of the Current
DA. Combine R6 Page 3 and these 2 bits as complete 10 bits Current
DA output data.
Bit 6 (URR8) : MSB of UART receiver data buffer.
Bit 7 (URT8) : MSB of UART transmitter data buffer.
7.2.16 RA CPU Power Saving, Main CLK Select, FSK, WDT Timer
Comparator Control, Tone 1 Generator
7.2.16.1 Page 0 Power Saving, Main CLK Select, FSK, WDT Timer
Bit 7
0
Bit 6
PLLEN
R/W-0
Bit 5
CLK1
R/W-0
Bit 4
CLK0
R/W-0
Bit 3
ROMRI FSKDATA
R/W-0
Bit 2
Bit 1
/CD
R
Bit 0
WDTEN
R/W-0
R/W-0
R
Bit 0 (WDTEN) : Watchdog control register
User can use WDTC instruction to clear the watchdog counter. The
counter's clock source is 32768/2 Hz. If the prescaler is assigned to
TCC, the Watchdog will time out by (1/32768 )*2 * 256 = 15.616ms. If
the prescaler is assigned to WDT, the time out will be more times
depending on the prescaler ratio.
0/1 → disable/enable
Bit 1 (/CD) : FSK carrier detect indication
0/1 → Carrier Valid/Carrier Invalid
It is a read only signal. If the FSK decoder detects the energy of the
marked or space signal, the Carrier signal will go to low level.
Otherwise it will go to high. Note that this should be in normal mode.
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
33
ELAN [ ELAN MICROELECTRONICS CORP ]
