EM78815
8-Bit Microcontroller
The controller is a CMOS device designed to support the Caller Number Deliver
feature which is offered by the Regional Bell Operating Companies. The FSK block
comprises one path: the signal path. The signal path consist of an input differential
buffer, a band pass filter, an FSK demodulator and a data valid with carrier detect
circuit.
In a typical application, user can use his own external ring detect output as a
triggering input to IO port. User can use this signal to wake up the chip by external
ring detect signal. Setting “0, 1” to R5 B4 and B3 (PCTRL1 & PCTRL0) of the RA
register activates the FSK decoder block. If B4 and B3 of register R5 is set to “0, 1”,
the FSK decoder block will be powered down.
The input buffer accepts a differential AC coupled input signal through the TIP and
RING input and feeds this signal to a band pass filter. Once the signal is filtered, the
FSK demodulator decodes the information and sends it to a post filter. The output
data is then made available at Bit 2 (FSKData) of register RA. This data, as sent by
the central office, includes the header information (alternate "1" and "0") and 150 ms
of marking which precedes the date, time and calling number. If no data is present,
the Bit 2 (Data) of register RA is held at “1” state. This is accomplished by a carrier
detect circuit which determines if the in-band energy is high enough. If the incoming
signal is valid, Bit 1 (/CD) of register RA will be “0” otherwise it will be held at “1”.
Thus the demodulated data is transferred to Bit 2 (Data) of register RA. If it is not,
then the FSK demodulator is blocked.
Bit 3 (ROMRI) : External Data ROM read data address auto_increase enable.
RO_IDEN
ROMRI
Result
Regardless Read/Write external Data ROM,
Address flag cannot increase or decrease.
0
×
Address flag will auto_increase or decrease
after a Read/Write of the external Data ROM.
1
1
0
1
Address flag will auto_increase or decrease
after a Write to the external Data ROM, but the address
flag is constant after reading the external Data ROM.
Bit 4 ~ Bit 5 (CLK0 ~ CLK1) : Main clock selection bits
User can choose different frequency for the main clock by CLK1 and CLK2. All the
clock selection is listed below.
PLLEN
CLK1
CLK0
Sub Clock
Main Clock
5.374MHz
1.7913MHz 1.7913MHz (Normal mode)
CPU Clock
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
32.768kHz
32.768kHz
5.374MHz (Normal mode)
32.768kHz 10.7479MHz 10.7479MHz (Normal mode)
32.768kHz
32.768kHz
32.768kHz
32.768kHz
32.768kHz
3.5826MHz 3.5826MHz (Normal mode)
Don’t care don’t care
Don’t care don’t care
Don’t care don’t care
Don’t care don’t care
Don’t care
Don’t care
Don’t care
Don’t care
32.768kHz (Green mode)
32.768kHz (Green mode)
32.768kHz (Green mode)
32.768kHz (Green mode)
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
35
ELAN [ ELAN MICROELECTRONICS CORP ]
