EM78815
8-Bit Microcontroller
Bit 6 (PLLEN) : PLL enable control bit
It is CPU mode control register. If PLL is enabled, the CPU will
operate in normal mode (high frequency, main clock), otherwise it
will run in green mode (low frequency, 32768 Hz).
0/1 → disable/enable
3.5826 MHz to analog circuit
2
× 1
÷
=>1.7913MHz
=>3.5826MHz
PLL
× 1.5=> 5.374MHz
× 3
1
=>10.7479MHz
switch
System clock
Sub-clock
32.768kHz
ENPLL
0
CLK1 ~ CLK0
Fig. 18 Relationship between 32.768kHz and PLL
Bit 7: Unused Register. Always keep this bit to 0, otherwise some un-expected
error will occur.
Wake-up Signal
Sleep Mode
Green Mode
Normal Mode
RA (7, 6) = (0, 0)
+ SLEP
RA (7, 6) = (x, 0)
no SLEP
RA (7, 6) = (x, 1)
no SLEP
TCC time out
Interrupt
Interrupt
IOCF Bit 0=1
And "ENI"
Counter 1 time out
IOCF Bit 1=1
And "ENI"
Counter 2 time out
IOCF Bit 2=1
And "ENI"
No function
No function
No function
(jump to Address 8 (jump to Address 8
at Page 0)
at Page 0)
Interrupt
Interrupt
(jump to Address 8 (jump to Address 8
at Page 0)
at Page 0)
Interrupt
Interrupt
(jump to Address 8 (jump to address 8
at Page 0)
at Page 0)
RESET and Jump
to Address 0
RESET and Jump
to Address 0
RESET and Jump
to Address 0
WDT time out
Port 7
Any one bit in IOCE
Page 0 = 1
Interrupt
Interrupt
RESET and Jump
to Address 0
(jump to Address 8 (jump to Address 8
at Page 0)
at Page 0)
And "ENI"
DED interrupt
IOCE page1 bit 6 = 1
And RF Bit 3 logic level
variation
(switch by EDGE bit)
And “ENI”
Interrupt
Interrupt
No function
(jump to Address 8 (jump to Address 8
at Page 0) at Page 0)
36 •
Product Specification (V2.4) 02.17.2006
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
