EM78815
8-Bit Microcontroller
7.2.14.3 Page 2 DTMF Receiver
Bit 7
CMPFLAG
R
Bit 6
STD
Bit 5
Bit 4
Bit 3
Q4
Bit 2
Q2
Bit 1
Q1
Bit 0
Q0
−
×
−
×
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0 ~ Bit 3 (Q1 ~ Q4) : DTMF receiver decoding data
These provide the code corresponding to the last valid tone-pair received (see code
table). The STD signal with steering output presents a logic high when a received
tone-pair has been registered and the Q4 ~ Q1 output latch updated, and generates
an interrupt (IOCF has enabled); returns to logic low when the voltage on ST/GT falls
below Vtst.
F low
F high
Key
DREN
Q4~Q1
697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941
Any
1209
1336
1477
1209
1336
1477
1209
1336
1477
1209
1336
1477
1633
1633
1633
1633
Any
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
××××
3
4
5
6
7
8
9
0
*
#
A
B
C
D
Any
Note: “×” means unknown
Bit 4~Bit 5 : Undefined Register
Bit 6 (STD) : Delayed steering output
Presents a logic high when a received tone-pair has been registered
and the output latch updated; returns to logic low when the voltage on
St/GT falls below Vtst.
0/1 → Data invalid/data valid
Be sure to open the main clock before using the DTMF receiver circuit. A logic ”0, 0”
applied to R5 Page 3 B 4 and B 3 will shut down power of the device to minimize the
power consumption in standby mode. It stops functions of the filters.
Product Specification (V2.4) 08.01.2004
(This specification is subject to change without further notice)
29
ELAN [ ELAN MICROELECTRONICS CORP ]
