EM77950
BB Controller
11.2 PWM Control Registers
As the PWM mode is defined, the related registers of this operation are shown below:
INTF (0x11): Interrupt flag
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADIF
RBFIF
PWM1IF PWM0IF
EINT1F
EINT0F
TCCOF
FRCOF
DT0L (0x21): Duty of PWM0 low byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DT07
DT06
DT05
DT04
DT03
DT02
DT01
DT00
DT0H (0x22): Duty of PWM0 high byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DT0F
DT0E
DT0D
DT0C
DT0B
DT0A
DT09
DT08
DL0L (0x25): Duty latch of PWM0 low byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DL07
DL06
DL05
DL04
DL03
DL02
DL01
DL00
DL0H (0x26): Duty latch of PWM0 high byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DL0F
DL0E
DL0D
DL0C
DL0B
DL0A
DL09
DL08
DT1L (0x27): Duty of PWM1 low byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DT17
DT16
DT15
DT14
DT13
DT12
DT11
DT10
DT1H (0x28): Duty of PWM1 high byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DT1F
DT1E
DT1D
DT1C
DT1B
DT1A
DT19
DT18
DL1L (0x2B): Duty latch of PWM1low byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DL17
DL16
DL15
DL14
DL13
DL12
DL11
DL10
DL2H (0x2C): Duty latch of PWM1 high byte
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DL1F
DL1E
DL1D
DL1C
DL1B
DL1A
DL19
DL18
The PWM duty cycle is defined by writing to the DTX register, and is latched from DTX
to DLX while TMRX is cleared. When DLX is equal to TMRX, the PWMX pin is cleared.
DTX can be loaded at any time. However, it cannot be latched into DLX until the
current value of DLX is equal to TMRX.
76 •
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
