EM77950
BB Controller
IMS2~IMS0 (Bit 2 ~ Bit 4): ADC configuration definition bit.
PTE PTE PTE PTE PTE PTE PTE PTE PTD PTD PTD PTD PTD PTD PTD PTD
IMS
7
F
A
A
A
A
A
A
A
A
6
E
A
A
A
A
A
A
A
A
5
D
D
A
A
A
A
A
A
A
4
C
D
A
A
A
A
A
A
A
3
B
D
D
A
A
A
A
A
A
2
A
D
D
A
A
A
A
A
A
1
0
7
6
5
4
3
2
1
0
ADC
000
001
010
011
100
101
110
111
9
8
7
6
5
4
3
2
1
0
D
D
D
A
A
A
A
A
D
D
D
A
A
A
A
A
D
D
D
D
A
A
A
A
D
D
D
D
A
A
A
A
D
D
D
D
D
A
A
A
D
D
D
D
D
A
A
A
D
D
D
D
D
D
A
A
D
D
D
D
D
D
A
A
D
D
D
D
D
D
D
A
D
D
D
D
D
D
D
A
CKR2~CKR0 (Bit 2 ~ Bit 0): AD conversion Rate control bits.
A/D Conversion Rate Unit: kHz
CKR2: CKR1:
CKR0
6MHz
12MHz
24MHz
48MHz
Divided Rate
Clock
Clock
Clock
Clock
Source
Source
Source
Source
000
001
010
011
100
101
110
111
÷ 2
÷ 4
250
125
62.5
31.3
15.6
7.8
500
250
125
62.5
31.3
15.6
7.8
1000
500
250
125
62.5
31.3
15.6
7.8
2000
1000
500
÷ 8
÷ 16
÷ 32
÷ 64
÷ 128
÷ 256
250
125
62.5
31.3
15.6
3.9
2.0
3.9
ADCCRR (0x97): ADC configuration register.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
AIPS3
Bit 2
Bit 1
AIPS1
Bit 0
ADRUN
ADIE
-
-
SIPA2
AIPS0
AIPS0~AIPS3 (Bits 0~3): Analog Input Select.
0000 = AN0;0001 = AN1; 0010 = AN2;0011 = AN3
0100 = AN4;0101 = AN5; 0110 = AN6;0111 = AN7
1000 = AN8;1001 = AN9; 1010 = ANA;1011 = ANB
1100 = ANC;1101 = AND; 1110 = ANE;1111 = ANF
They can only be changed when the ADIF bit and the ADRUN bit are both
LOW.
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
• 73