EM77950
BB Controller
ADCF
ADCE
ADCD
ADCC
ADCB
ADCA
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
Vref
ADC
( successive approximation )
Start to Convert
Fsco
8-1
MUX
Power Down
2
1
7
4
3
3
2
1
0
0
7
6
5
4
3
2
1
0
7
5
4
AIPS[0:3]
ADDATA
IMS[0:2]
CKR[0:2]
ADRUN
ADE
ADIF
ADE
DATA BUS
Fig.10 Analog-to-Digital Conversion Functional Block Diagram
10.1 ADC Control Registers
As the ADC mode is defined, the related registers of this operation are shown below:
INTF (0X11): Interrupt flag,
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADIF
RBFIF
PWM1IF PWM0IF
EINT1F
EINT0F
TCCOF
FRCOF
ADDATA (0x1F): ADC 8-bit data.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADD7
ADD6
ADD5
ADD4
ADD3
ADD2
ADD1
ADD0
When the A/D conversion is completed, Bit 7 ~ Bit 0 are loaded to the
ADDATA [7:0]. The ADCRUN bit is cleared, and the ADIF is set.
PRIE (0x80): Peripherals enable control
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPIE
-
BBE
ADE
PWM1E
PWM0E
TCCE
FRCE
ADCAIS (0x96): ADC analog input pin select and conversion rate select.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
IMS2
IMS1
IMS0
CKR2
CKR1
CKR0
72 •
Product Specification (V1.0) 10.09.2007
(This specification is subject to change without further notice)
ELAN [ ELAN MICROELECTRONICS CORP ]
