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EM77950 参数 Datasheet PDF下载

EM77950图片预览
型号: EM77950
PDF下载: 下载PDF文件 查看货源
内容描述: BB控制器 [BB Controller]
分类和应用: 控制器
文件页数/大小: 102 页 / 928 K
品牌: ELAN [ ELAN MICROELECTRONICS CORP ]
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EM77950  
BB Controller  
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Programmed the same clock rate and the same clock edge to latch on both the  
master device and slave device.  
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The received byte will replace the corresponding transmitted byte.  
The RBFIF bit will be set, as the SPI operation is completed.  
Timing is shown in Fig. 9-2.  
SCK:  
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Serial Clock.  
Generated by a master device.  
Synchronize the data communication on both the SDI pin and the SDO pin.  
The CES used to select the edge to communicate.  
The SBR0~SBR2 used to determine the baud rate of communication.  
The ES, SBR0, SBR1, and SBR2 bit have no effect in the slave mode.  
Timing is shown in Fig. 9-2  
SDO:  
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Serial Data Out  
Transmit serially  
Programmed the same clock rate and the same clock edge to latch on both the  
master device and slave device.  
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The received byte will replace the transmitted byte.  
The SPIS bit will be reset, as the SPI operation is completed.  
Timing is shown in Fig. 9-2.  
10 Analog to Digital Converter (ADC)  
The analog-to-digital circuitry consists of one 16-to-1 multiplexer, two control registers  
(ADCAIS and ADCCR), one data register (ADDATA) and one ADC calculator with 8-bit  
resolution. The functional block diagram of the ADC is shown in Fig. 10. Port D [7:0]  
and Port E [7:0] can be selected as either normal digital I/O ports or analog input ports.  
A maximum of 16 analog input pins can be selected by ADCAIS register [5:3], IMS3  
~IMS0 bits. Control bits, AIPS3 ~ AIPS0, of ADCCR [3:0] are then used to select the  
ADC input channel that will supply analog signal to ADC calculator. CKR2 ~ CKR0  
control bits are used to select the desired conversion rate. The ADC module, then,  
utilizes successive approximation to convert the unknown analog signal into an 8-bit  
digital output value. Finally, the 8-bit result is fed to the ADDATA register. If the ADC  
interrupt is enabled, the ADC interrupt flag will be set to “1” as the analog-to-digital  
conversion is completed.  
Product Specification (V1.0) 10.09.2007  
(This specification is subject to change without further notice)  
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