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HM5225805BLTT-75 参数 Datasheet PDF下载

HM5225805BLTT-75图片预览
型号: HM5225805BLTT-75
PDF下载: 下载PDF文件 查看货源
内容描述: LVTTL 256M SDRAM接口的133 MHz / 100 MHz的4 Mword 】 16位】 4银行/ 8 - Mword 】 8位】 4银行/ 16 Mword 】 4位】 4银行PC / 133 , PC / 100 SDRAM [256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器PC时钟
文件页数/大小: 63 页 / 454 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6  
Auto Precharge  
Read with auto-precharge: In this operation, since precharge is automatically performed after completing a  
read operation, a precharge command need not be executed after each read operation. The command executed  
for the same bank after the execution of this command must be the bank active (ACTV) command. In  
addition, an interval defined by lAPR is required before execution of the next command.  
CAS latency  
Precharge start cycle  
3
2
2 cycle before the final data is output  
1 cycle before the final data is output  
Burst Read (Burst Length = 4)  
CLK  
ACTV  
READ A  
ACTV  
CL=2 Command  
DQ (input)  
l
RAS  
out0  
out1  
out2  
out3  
l
APR  
CL=3 Command  
DQ (input)  
ACTV  
READ A  
ACTV  
l
RAS  
out0  
out1  
out2  
out3  
l
APR  
Note: Internal auto-precharge starts at the timing indicated by " ".  
And an interval of t  
(l  
) is required between previous active (ACTV) command and internal precharge  
"
".  
RAS RAS  
Data Sheet E0082H10  
25  
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