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HM5225805BLTT-75 参数 Datasheet PDF下载

HM5225805BLTT-75图片预览
型号: HM5225805BLTT-75
PDF下载: 下载PDF文件 查看货源
内容描述: LVTTL 256M SDRAM接口的133 MHz / 100 MHz的4 Mword 】 16位】 4银行/ 8 - Mword 】 8位】 4银行/ 16 Mword 】 4位】 4银行PC / 133 , PC / 100 SDRAM [256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器PC时钟
文件页数/大小: 63 页 / 454 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6  
Write operation: Burst write or single write mode is selected by the OPCODE (BA1, BA0, A12, A11, A10,  
A9, A8) of the mode register.  
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write  
starts in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can  
be set to 1, 2, 4 and 8, like burst read operations. The write start address is specified by the column address  
and the bank select address (BA0/BA1) at the write command set cycle.  
CLK  
t
RCD  
Command  
Address  
ACTV  
Row  
WRIT  
Column  
in 0  
in 0  
BL = 1  
in 1  
in 1  
in 1  
BL = 2  
BL = 4  
BL = 8  
Din  
in 3  
in 2  
in 2  
in 0  
in 0  
in 5  
in 6 in 7  
in 3 in 4  
CAS Latency = 2, 3  
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write  
operation, data is only written to the column address and the bank select address (BA0/BA1) specified by the  
write command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).  
CLK  
t
RCD  
Command  
WRIT  
ACTV  
Row  
Column  
in 0  
Address  
Din  
Data Sheet E0082H10  
24  
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