HM5225165B/HM5225805B/HM5225405B-75/A6/B6
Self-refresh entry [SELF]: When this command is input during the IDLE state, the SDRAM starts self-
refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since self-
refresh is performed internally and automatically, external refresh operations are unnecessary.
Power down mode entry: When this command is executed during the IDLE state, the SDRAM enters power
down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit.
Self-refresh exit: When this command is executed during self-refresh mode, the SDRAM can exit from self-
refresh mode. After exiting from self-refresh mode, the SDRAM enters the IDLE state.
Power down exit: When this command is executed at the power down mode, the SDRAM can exit from
power down mode. After exiting from power down mode, the SDRAM enters the IDLE state.
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of
the SDRAM.
The following table assumes that CKE is high.
Current state
CS
H
L
RAS CAS WE
Address
Command
DESL
Operation
Precharge
×
H
H
H
L
×
H
L
×
×
Enter IDLE after tRP
Enter IDLE after tRP
H
H
L
×
NOP
L
BA, CA, A10 READ/READ A ILLEGAL*4
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*4
ILLEGAL*4
NOP*6
L
H
H
L
H
L
BA, RA
ACTV
L
L
BA, A10
PRE, PALL
REF, SELF
MRS
L
L
H
L
×
ILLEGAL
ILLEGAL
NOP
L
L
L
MODE
Idle
H
L
×
H
H
H
L
×
H
L
×
×
DESL
H
H
L
×
NOP
NOP
L
BA, CA, A10 READ/READ A ILLEGAL*5
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*5
L
H
H
L
H
L
BA, RA
BA, A10
×
ACTV
Bank and row active
NOP
L
L
PRE, PALL
REF, SELF
MRS
L
L
H
L
Refresh
L
L
L
MODE
Mode register set
Data Sheet E0082H10
14
ELPIDA [ ELPIDA MEMORY ]
