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HM5225805BLTT-75 参数 Datasheet PDF下载

HM5225805BLTT-75图片预览
型号: HM5225805BLTT-75
PDF下载: 下载PDF文件 查看货源
内容描述: LVTTL 256M SDRAM接口的133 MHz / 100 MHz的4 Mword 】 16位】 4银行/ 8 - Mword 】 8位】 4银行/ 16 Mword 】 4位】 4银行PC / 133 , PC / 100 SDRAM [256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器PC时钟
文件页数/大小: 63 页 / 454 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6  
CKE Truth Table  
CKE  
Current state  
Command  
n - 1  
H
L
n
L
CS  
×
RAS CAS WE Address  
Active  
Clock suspend mode entry  
Clock suspend  
×
×
×
L
L
H
×
H
×
H
×
×
×
×
L
L
H
×
H
×
H
×
×
×
×
×
×
×
×
×
×
×
×
×
Any  
L
×
×
Clock suspend  
Clock suspend mode exit  
Auto-refresh command (REF)  
Self-refresh entry (SELF)  
Power down entry  
L
H
H
L
×
×
Idle  
Idle  
Idle  
H
H
H
H
L
L
H
H
H
×
L
L
L
L
H
L
Self refresh  
Power down  
Self refresh exit (SELFX)  
Power down exit  
H
H
H
H
H
×
L
H
L
L
H
×
L
H
Note: H: VIH. L: VIL. ×: VIH or VIL.  
Clock suspend mode entry: The SDRAM enters clock suspend mode from active mode by setting CKE to  
Low. If command is input in the clock suspend mode entry cycle, the command is valid. The clock suspend  
mode changes depending on the current status (1 clock before) as shown below.  
ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining  
the bank active status.  
READ suspend and READ with Auto-precharge suspend: The data being output is held (and continues to  
be output).  
WRITE suspend and WRIT with Auto-precharge suspend: In this mode, external signals are not  
accepted. However, the internal state is held.  
Clock suspend: During clock suspend mode, keep the CKE to Low.  
Clock suspend mode exit: The SDRAM exits from clock suspend mode by setting CKE to High during the  
clock suspend state.  
IDLE: In this state, all banks are not selected, and completed precharge operation.  
Auto-refresh command [REF]: When this command is input from the IDLE state, the SDRAM starts auto-  
refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.) During the  
auto-refresh operation, refresh address and bank select address are generated inside the SDRAM. For every  
auto-refresh cycle, the internal address counter is updated. Accordingly, 8192 times are required to refresh  
the entire memory. Before executing the auto-refresh command, all the banks must be in the IDLE state. In  
addition, since the precharge for all banks is automatically performed after auto-refresh, no precharge  
command is required after auto-refresh.  
Data Sheet E0082H10  
13