HM5225165B/HM5225805B/HM5225405B-75/A6/B6
VSS and VSSQ (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for the
output buffer.)
Command Operation
Command Truth Table
The SDRAM recognizes the following commands specified by the CS, RAS, CAS, WE and address pins.
CKE
A0
CS RAS CAS WE BA0/BA1 A10 to A12
Command
Symbol
DESL
NOP
n - 1 n
Ignore command
No operation
H
H
H
H
H
H
H
H
H
×
×
×
×
×
×
×
×
×
V
×
H
L
L
L
L
L
L
L
L
L
L
×
×
H
L
×
×
×
×
×
H
H
H
H
H
L
H
H
H
L
×
×
Column address and read command READ
V
V
V
V
V
V
×
L
V
V
V
V
V
×
Read with auto-precharge
READ A
L
H
L
Column address and write command WRIT
L
Write with auto-precharge
WRIT A
L
L
H
V
L
Row address strobe and bank active ACTV
H
H
H
L
H
L
Precharge select bank
Precharge all bank
Refresh
PRE
L
PALL
L
L
H
×
×
REF/SELF H
MRS
L
H
L
×
×
Mode register set
H
L
L
V
V
V
Note: H: VIH. L: VIL. ×: VIH or VIL. V: Valid address input
Ignore command [DESL]: When this command is set (CS is High), the SDRAM ignore command input at
the clock. However, the internal status is held.
No operation [NOP]: This command is not an execution command. However, the internal operations
continue.
Column address strobe and read command [READ]: This command starts a read operation. In addition,
the start address of burst read is determined by the column address (AY0 to AY8; HM5225165B, AY0 to
AY9; HM5225805B, AY0 to AY9, AY11; HM5225405B) and the bank select address (BS). After the read
operation, the output buffer becomes High-Z.
Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a
burst read with a burst length of 1, 2, 4 or 8.
Data Sheet E0082H10
10
ELPIDA [ ELPIDA MEMORY ]
