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HM5225805BLTT-75 参数 Datasheet PDF下载

HM5225805BLTT-75图片预览
型号: HM5225805BLTT-75
PDF下载: 下载PDF文件 查看货源
内容描述: LVTTL 256M SDRAM接口的133 MHz / 100 MHz的4 Mword 】 16位】 4银行/ 8 - Mword 】 8位】 4银行/ 16 Mword 】 4位】 4银行PC / 133 , PC / 100 SDRAM [256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器PC时钟
文件页数/大小: 63 页 / 454 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6  
Column address strobe and write command [WRIT]: This command starts a write operation. When the  
burst write mode is selected, the column address (AY0 to AY8; HM5225165B, AY0 to AY9; HM5225805B,  
AY0 to AY9, AY11; HM5225405B) and the bank select address (BA0/BA1) become the burst write start  
address. When the single write mode is selected, data is only written to the location specified by the column  
address (AY0 to AY8; HM5225165B, AY0 to AY9; HM5225805B, AY0 to AY9, AY11; HM5225405B) and  
the bank select address (BA0/BA1).  
Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a  
burst write with a length of 1, 2, 4 or 8, or after a single write operation.  
Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by  
BA0/BA1 (BS) and determines the row address (AX0 to AX12). When BA0 and BA1 are Low, bank 0 is  
activated. When BA0 is Low and BA1 is High, bank 1 is activated. When BA0 is High and BA1 is Low,  
bank 2 is activated. When BA0 and BA1 are High, bank 3 is activated.  
Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by  
BA0/BA1. If BA0 and BA1 are Low, bank 0 is selected. If BA0 is Low and BA1 is High, bank 1 is selected.  
If BA0 is High and BA1 is Low, bank 2 is selected. If BA0 and BA1 are High, bank 3 is selected.  
Precharge all banks [PALL]: This command starts a precharge operation for all banks.  
Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation,  
the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.  
Mode register set [MRS]: The SDRAM has a mode register that defines how it operates. The mode register  
is specified by the address pins (A0 to BA0 and BA1) at the mode register set cycle. For details, refer to the  
mode register configuration. After power on, the contents of the mode register are undefined, execute the  
mode register set command to set up the mode register.  
Data Sheet E0082H10  
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