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HM5225805BLTT-75 参数 Datasheet PDF下载

HM5225805BLTT-75图片预览
型号: HM5225805BLTT-75
PDF下载: 下载PDF文件 查看货源
内容描述: LVTTL 256M SDRAM接口的133 MHz / 100 MHz的4 Mword 】 16位】 4银行/ 8 - Mword 】 8位】 4银行/ 16 Mword 】 4位】 4银行PC / 133 , PC / 100 SDRAM [256M LVTTL interface SDRAM 133 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank /16-Mword 】 4-bit 】 4-bank PC/133, PC/100 SDRAM]
分类和应用: 存储内存集成电路光电二极管动态存储器PC时钟
文件页数/大小: 63 页 / 454 K
品牌: ELPIDA [ ELPIDA MEMORY ]
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HM5225165B/HM5225805B/HM5225405B-75/A6/B6  
DQM Truth Table (HM5225165B)  
CKE  
Command  
Symbol  
n - 1  
H
n
×
×
×
×
DQMU DQML  
Upper byte (DQ8 to DQ15) write enable/output enable ENBU  
Lower byte (DQ0 to DQ7) write enable/output enable ENBL  
Upper byte (DQ8 to DQ15) write inhibit/output disable MASKU  
Lower byte (DQ0 to DQ7) write inhibit/output disable MASKL  
L
×
H
×
×
L
×
H
H
H
H
Note: H: VIH. L: VIL. ×: VIH or VIL.  
Write: IDID is needed.  
Read: IDOD is needed.  
DQM Truth Table (HM5225805B/HM5225405B)  
CKE  
n - 1  
H
Command  
Symbol  
ENB  
n
×
×
DQM  
Write enable/output enable  
Write inhibit/output disable  
L
MASK  
H
H
Note: H: VIH. L: VIL. ×: VIH or VIL.  
Write: IDID is needed.  
Read: IDOD is needed.  
The SDRAM can mask input/output data by means of DQM, DQMU/DQML.  
DQMU masks the upper byte and DQML masks the lower byte. (HM5225165B)  
During reading, the output buffer is set to Low-Z by setting DQM, DQMU/DQML to Low, enabling data  
output. On the other hand, when DQM, DQMU/DQML is set to High, the output buffer becomes High-Z,  
disabling data output.  
During writing, data is written by setting DQM, DQMU/DQML to Low. When DQM, DQMU/DQML is set  
to High, the previous data is held (the new data is not written). Desired data can be masked during burst read  
or burst write by setting DQMU/DQML. For details, refer to the DQM, DQMU/DQML control section of the  
SDRAM operating instructions.  
Data Sheet E0082H10  
12  
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