HM5225165B/HM5225805B/HM5225405B-75/A6/B6
Pin Functions
CLK (input pin): CLK is the master clock input to this pin. The other input signals are referred at CLK
rising edge.
CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RAS, CAS, and WE (input pins): Although these pin names are the same as those of conventional DRAMs,
they function in a different way. These pins define operation commands (read, write, etc.) depending on the
combination of their voltage levels. For details, refer to the command operation section.
A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active
command cycle CLK rising edge. Column address (AY0 to AY8; HM5225165B, AY0 to AY9;
HM5225805B, AY0 to AY9, AY11; HM5225405B) is determined by A0 to A8, A9 or A11 (A8;
HM5225165B, A9; HM5225805B, A9, A11; HM5225405B) level at the read or write command cycle CLK
rising edge. And this column address becomes burst access start address. A10 defines the precharge mode.
When A10 = High at the precharge command cycle, all banks are precharged. But when A10 = Low at the
precharge command cycle, only the bank that is selected by BA0/BA1 (BS) is precharged. For details refer to
the command operation section.
BA0/BA1 (input pin): BA0/BA1 are bank select signal (BS). The memory array of the HM5225165B,
HM5225805B, the HM5225405B is divided into bank 0, bank 1, bank 2 and bank 3. HM5225165B contain
8192-row × 512-column × 16-bit. HM5225805B contain 8192-row × 1024-column× 8-bit. HM5225405B
contain 8192-row × 2048-column × 4-bit. If BA0 is Low and BA1 is Low, bank 0 is selected. If BA0 is Low
and BA1 is High, bank 1 is selected. If BA0 is High and BA1 is Low, bank 2 is selected. If BA0 is High and
BA1 is High, bank 3 is selected.
CKE (input pin): This pin determines whether or not the next CLK is valid. If CKE is High, the next CLK
rising edge is valid. If CKE is Low, the next CLK rising edge is invalid. This pin is used for power-down
mode, clock suspend mode and self refresh mode.
DQM, DQMU/DQML (input pins): DQM, DQMU/DQML controls input/output buffers.
Read operation: If DQM, DQMU/DQML is High, the output buffer becomes High-Z. If the DQM,
DQMU/DQML is Low, the output buffer becomes Low-Z. (The latency of DQM, DQMU/DQML during
reading is 2 clocks.)
Write operation: If DQM, DQMU/DQML is High, the previous data is held (the new data is not written). If
DQM, DQMU/DQML is Low, the data is written. (The latency of DQM, DQMU/DQML during writing is 0
clock.)
DQ0 to DQ15 (DQ pins): Data is input to and output from these pins (DQ0 to DQ15; HM5225165B, DQ0
to DQ7; HM5225805B, DQ0 to DQ3; HM5225405B).
VCC and VCCQ (power supply pins): 3.3 V is applied. (VCC is for the internal circuit and VCCQ is for the
output buffer.)
Data Sheet E0082H10
9
ELPIDA [ ELPIDA MEMORY ]
